We are looking for a innovative problem solver with experience in developing Analyzers, and Elaborators for Verilog and VHDL. You will apply these techniques to a parallel hardware description language
(Verilog/VHDL) Compiler that targets a special purpose VLIW architecture for simulation.
Qualifications
Requirements:
o MS CS or equivalent with 3-6+ years experience
o Experience in multi-person, large software project teams
o Software Development experience in a Unix/C++ Environment
o Experience in developing Mixed Language Elaborators
Preferred Experience:
o Knowledge of HDL Semantics and Simulation Algorithms
o Experience with AST/IR Transforms
We are looking for a innovative problem solver with experience implementing graph algorithms in areas such as scheduling, and partitioning. You will apply these techniques to a parallel hardware description language (Verilog/VHDL) Compiler that targets a special purpose VLIW architecture for simulation.
Qualifications
Requirements:
o MS CS or equivalent with 6+ years or PhD with 0-2 years
o Experience in multi-person, large software project teams
o Software Development experience in a Unix/C++ Environment
o Experience in developing Graph Algorithms
Preferred Experience in one or more of the following topics:
o Partitioning/Scheduling of Parallel Programs
o Scheduling for VLIW Processor
o Knowledge of HDL Semantics and Simulation Algorithms
