Required Skills: IR and backend optimizations, VLIW/DSP/loop optimizations, integrated scheduling and register allocation for clustered register file architectures, power optimization, Unix/C++/Python
What will set the successful candidate apart from the crowd will be breadth of knowledge, familiarity with Python, Pyrex and Swig bindings and the ability to solve challenging problems independently. MS/PhD or 5+ years of relevant experience required.
Local (East Bay) candidates preferred. Applicant must live/relocate within commuting distance of our office in Berkeley, CA.
Principals only!!
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