We are looking for a innovative problem solver with experience in developing compiler optimizations and program transformations. You will apply these techniques to a parallel hardware description language (Verilog/VHDL) Compiler that targets a special purpose VLIW architecture for simulation.
Qualifications
Preferred Experience:
o Loop Restructuring/Optimization
o Knowledge of HDL Semantics and Simulation Algorithms
o Partitioning/Scheduling of Parallel Programs
Requirements:
o MS CS or equivalent with 6+ years or PhD with 0-2 years
o Experience in multi-person, large software project teams
o Software Development experience in a Unix/C++ Environment
o Experience in developing Graph Algorithms
o Experience in developing Code Optimization Phases
o Dataflow Analysis
